Most digital electronic components sold are tested by their manufacturer several times before being shipped.
Component testers have two functions: firstly, generating digital signals, at logic 0 or logic 1, for example, and, secondly, verifying the presence of output transitions by comparison with a pre-established test table. The timing and the levels of the signals generated and the signals compared are programmable. As a general rule, a component tester must generate and/or compare signals simultaneously at all the functional pins of the component under test.
Defining the signals to be generated and/or compared is usually extremely complex. Testing a microprocessor can entail strings of several million 0 or 1 bits in the same sequence. To define the signals, the concept of period is used to determine a time band within which a simpler signal is defined. This signal is decomposed into timing data, also known as a time marker, and an event, for example a transition.
A functional test is therefore executed by scanning a test programming memory in which each line corresponds to a period and the content of which represents timing and event data defining the signal within the period for each pin. The timing and event data is complemented by, among other things, an instruction which controls the scanning of the test programming memory. This instruction is common to all of the functional pins of the circuit under test. The most common instruction is that to read the next line (instruction INC).
This architecture based on scanning a memory is deterministic in the sense that it assumes that it is possible to know a priori exactly what will happen at a given time at the pins of the electronic circuit under test.
A logic component tester has various parts:
a programming system, PA1 a test circuit for each pin including a system for generating stimuli, i.e. forcing signals, which must be applied to the pin in question and a system for comparing response signals from the component, PA1 one or more interface systems, measurement heads, for adapting the stimuli to the constraints of the component to be verified.
The number of stimuli generators/comparators can be between 32 and 1 024; in the present context there is a limit of 256 generators/comparators. There can be two measurement heads, for example, each including 256 adapters.
To optimize the cost of the test and the surface area occupied by the tester, it is possible to connect identical pins of a plurality of heads to the same test circuit, i.e. to the same stimuli generation/comparison system. Multiplexers (one per signal and per pin) at the output of the generation/comparison part generally route the signals to one head or the other. Accordingly, one component is tested on head No.1 while another component is being manipulated on head No.2, and vice versa. This increases the capacity of the tester by adding one head. Typically, adding a head doubles the capacity of the tester if the test time is identical to the manipulation time.
In the case of identical components, testers with two heads used simultaneously have been proposed in which the same stimuli are generated in parallel at both heads. Likewise, the received response signals are compared with a table simultaneously by different circuits. The tester then generates two results: that from head No.1 and that from head No.2. Accordingly, the capacity of the tester is actually doubled, simply by duplicating the generation circuits and the table comparison circuits, given that the table is the same for head No.1 as for head No.2, since the signals generated and the components under test are identical.
Parallel testing therefore enables n components to be tested simultaneously in a similar way to testing a single component. The simultaneous testing can of course be done on the same head or on more than one head. The present invention is addressed to both of these alternatives.
In practice, electronic components are tested in parallel, in a manner that it is known in itself, by means of test circuits like that shown in FIG. 1 in the case of two components, each of these circuits testing identical pins on each component.
The generation system of the test circuit from FIG. 1 includes two forcing circuits adapted to apply stimuli, i.e. forcing signals, to identical pins of the components under test, said forcing signals being formed by two timing generators controlled by the programming memory, not shown in FIG. 1.
The comparison system includes two comparator circuits receiving from the pins response signals to the forcing signals, said response signals being compared to reference signals supplied by two other timing generators from a table supplied by the test programming memory.
In the remainder of this specification, the expression "test signal" is used non-specifically to refer to a forcing signal or to a response signal.
With test circuits of the type known in itself shown in FIG. 1, the pins of one component are in one-to-one correspondence with the same pins of the other component. This particular method of parallel testing, in which identical pins are forced and compared synchronously, is well-suited to components whose operation is totally known and identical from one component to another.
However, there are digital components, for example microprocessors, in which the logic state of the outputs of a given component does not correspond exactly in time to the logic state of the same outputs of another (even though identical) component. This situation is encountered in particular with components that include clocks which introduce random phase-shifts of the signals that are too large to be compensated by the limited adjustment dynamic range of the timing generators.